Newsroom
New video for Handling multiple FPGA boards is available.
April 15th, 2018
New feature to support multiple FPGA boards is added to VAXEL ver1.0.0. This video introduces how to handle multiple FPGA boards by CLI.
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Whitepaper is now available – Enabling Image Process ASIC HDL verification with real-size test data
April 1st, 2018
Enabling Image Process ASIC HDL verification with real-size test data without suffering from slowness of Simulators or high cost of Emulators or having to learn FPGA synthesis.
AUTHOR: Yasu Sakakibara, CTO
Image Process hardware design verification requires a set of very large test data. This has become more true
with the recent increase in the frame sizes from FHD to 4K, 8K, and larger. RTL designers, however, are
forced to conduct design verifications with reduced-size test data for two reasons:first, because today’s
Simulators take a long time to run large test data, and second, because the hardware emulation tools from
the EDA vendors are just too expensive for most of the projects……………
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Released version 1.0.0 with new features
March 15th, 2018
Additional main features
Support for Multiboards
Wave monitor in each layer
Released the 1st VAXEL
November 21st, 2017
The 1st VAXEL is now available.
Released product overview
July 16th, 2017
Released VAXEL product overview. You can download this document from download page.