Now we provide

RISC-V Validations and Verifications with iTGV / VAXEL

Design Verification Services

FPGA Automation Solution

  •   Speeds up IP and subsystem design verification
  •   Simplifies full range of FPGA operations with intuitive GUI.
  •   Empowers software engineers to participate in the verification.
  •   UVM workflow compatibility

Intelligent Test Generator

  •   Compresses your test cases to the minimal number
  •   New “constrained direct” approach to achieve 100% coverage
  •   Gives full trace-ability to visibility for test management
  •   GUI for test generation and management

VAXEL-ZERO-EZ-BZ matrix

Find out what VAXEL model fits best for you

Select a description that matches your project best


VAXEL-ZERO VAXEL-EZ VAXEL-BZ
Automation of FPGA Synthesis Processor Only Yes Yes
Pre-qualified verification IP blocks - Yes Yes
Full control of the FPGA and test administration from Windows PC Yes Yes Yes
Support CLI and Python for Hostware Yes Yes Yes
Supports C for application processor Yes Yes Yes
Support EDA simulators (VCS/Incisive) - - Yes
UVM simulaion environment - - Yes
Assertion and waveform tools - - Yes
HDMI data IF / Hash calculator IP - - Yes
Supported target boards Zybo Z7, Eclypse Z7 Zybo Z7, Eclypse Z7 Zybo Z7, Eclypse Z7
ZC702, ZC706, ZCU102, VCK190
Pricing $499 $999 Contact Us

VAXEL GUI

System setup

Configurations

Generate files for synthesis

Run application

VAXEL Comparison table

VAXEL Emulator FPGA prototyping
Primary purpose Block, subsystem level RTL & IP verification Chip & system level verification System level verification
Design Phase Early to late phases Mid to late phases Late phase only
Use Environment Desktop of RTL designers & verification engineers Dedicated environment with power and cooling requirement Specialized FPGA board
Skill Required No FPGA knowledge and skills needed, software engineers can participate in verification Resource scheduling and management skills, emulator knowledge and skills desired FPGA specialist required, design must be modified to fit in the FPGA prototyping requirement
Design size < 6Mgates (Not VAXEL limitation) Depends on emulator capacity Depends on FPGA sizes
Design Ecosystem UVM UVM Independent
Cost of Owership Very low High Medium

No more FPGA expertise needed

NO LONGER NEEDED

Complex steps of FPGA/Hardware expertise with standard tools

  •   Generate place & route constraints for synthesis
  •   Definition of DUT inputs and outputs
  •   Define how to control the DUT
  •   Understand bus protocols such as AXI
  •   Write bitstream

VAXEL COMPONENTS

Components Description
VAXEL Hostware Administrative console that runs on Windows PC or Linux connecting to FPGA board via USB or Ethernet
Application Uploader Uploads C program (Application) to one of the MPUs (ARM) on FPGA
Python Library and V-CLI Allows Python program to be executed on the Hostware (VAXEL original CLI is provided)
VAXEL Coreware Runs on MPU (ARM) on FPGA and manages all communications to and from Hostware
VAXEL Verification IPs Over 60 pre-validated verification IP blocks choose from

VAXEL VERIFICATION IPs

Interface IPs

  •   Data read/write interface
  •   Asynchronous bridge (AXI to AXI/AHB/APB)
  •   Memory block
  •   Register interface
  •   RAM wrapper
  •   HDMI data IF

Debugging IPs

  •   Assertion interface block
  •   Wave monitor
  •   Hash block
  •   Simulation models
  •   UVM simulation models

VAXEL CLI/Python and C libraries

Classification

  •   Memory management basic
  •   Memory management property
  •   Register and memory access
  •   Load/Save
  •   Memory copy
  •   Bitstream handling
  •   Reset control
  •   Clock control
  •   Interrupt handling
  •   Trigger control
  •   Application program handling
  •   Checksum
  •   License control

VAXEL Work Flow

1. Build "VAXEL Environment" on Simulator and run the smoke test

2. When smoke test passes, move all verification to VAXEL

Note: Testbench can be compatible and interchangeable between UVM and VAXEL

VAXEL Patners

Supports ZC702, ZC706, ZCU102 and VCK190
Supports Eclypse Z7 and Zybo Z7

VAXEL Benefits

Productivity gain

Application Design size Budgeted Verification time Actual Verification time with VAXEL Productivity Gain
Image processing 700K 10 weeks 2 weeks 5x
Video Surveillance 1M 8 weeks 2 weeks 4x
Computer Vision 2M 12 weeks 3 weeks 4x

Performance comparison with simulator

Application Simulator VAXEL Productivity
FPU 97500sec 228s 427x
4K Image procesing 7200sec 50s 140x

VAXEL News

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