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Improving Verification Productivity by Bringing Precision and Automation to Test-Suite Generation

AUTHOR: Jun Takara, SVP Engineering

In today’s world of coverage-driven verification (CDV), verification engineers use both Directed and Constrained Random approaches to generate test suites (a.k.a. test patterns or test vectors). The Directed approach is usually chosen to start off with feature-specific verification processes because of its simplicity and ease of use. Typically shortly after, engineers elect to switch to the Constrained Random approach because it generates test suites to cover many features efficiently. The Directed approach is easy to set up and is precise in terms of generating test suites to cover the target parameter combinations. However, it can quickly become labor intensive as it requires considerable manual work to generate many test suites for each of the features. The Constrained Random approach automatically generates test suites. However, it is a wasteful methodology by nature, and as the coverage nears the target, its “hit rate” significantly worsens. This condition results in requiring substantially more time than truly needed. Having to use both Directed and Constrained Random approaches is not efficient, to say the least. I, a nearly 20-year veteran in the register-transfer level design verification space, view it as a pain point…………….. CONTINUE READING

7 BIG BENEFITS OF VAXEL, THE SUPER MINI-EMULATOR

“IT IS REALLY AN EMULATOR — ONLY YOUR DUT MUST FIT IN AN FPGA.”

VAXEL is a software solution that converts various FPGA evaluation boards into Super Mini-Emulator. Since its original release in Japan in 2017, multiple major Japanese OEMs are enjoying the savings in time and money which VAXEL brought to their projects. Check out below the list of VAXEL’s 7 big benefits!

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San Jose, CA, August 20, 2018 – VAXEL Incorporated, the developer of the innovative verification acceleration tool, VAXEL, has announced today that it added the Xilinx, Zynq UltraScale Evaluation board to its lineup of supported FPGA boards.

Tadd Matsuoka, CEO, VAXEL Incorporated stated that “This marks a significant addition to our block-level-focus RTL verification acceleration tool. Addition of the UltraScale EK-U1-ZCU102-G will increase the DUT size that we can verify from 4 million gates to 6 million gates.”

VAXEL previously supported ZC702 and ZC706 both from Xilinx.

“Our architecture is FPGA agnostic. Therefore, we are always trying to support more popular FPGA boards in the market. Xilinx has been our choice and they have been a very good partner to us too.” added Matsuoka.

The VAXEL suite comes with 4 piece set of software: 1. VAXEL Console, a Windows application that includes FPGA Synthesis automation tools with the features to execute the verification from the host PC, 2. VAXEL Firm, an ARM firmware that installs at one of the ARM cores on the FPGA board and translates commands and requests from VAXEL Console and configures the FPGA, 3. Pre-qualified hardware IP blocks, and 4. A set of software libraries and interfaces to enable C and Python engineers to have additional contribution during the RTL verification phase.

The biggest benefit that VAXEL offers is the speed of test execution, thanks to the FPGA boards, with an additional significant benefit which is the ease of set up. With the software suite above, the setting up of the Test Bench becomes very easy allowing, furthermore, reuse of the set-up assets avoiding thus a waste of cost and time. This is a paradigm shift from the UVM and System Verilog world of verification.

VAXEL fits especially well in ASIC projects targeted for image processing, sensor ASICS, and AI chips because they frequently require a large test data set and numerous test cases where increasing the test coverage is not the most important goal.

VAXEL is architected such that it can connect an unlimited number of FPGA boards via USB and as such can run verification of multiple blocks. It also comes with assertion IPs and waveform extraction IPs.

VAXEL is just like a mini-Emulator that is extremely cost effective and this has been proven by a handful of Japanese image giants.

About VAXEL Inc.
VAXEL Inc was founded by a group of top verification engineers from Japan who provided design verification services to major Japanese OEMs for over 10 years. The verification acceleration tool VAXEL was invented by Yasu Sakakibara CTO and released to the market in 2017. The company has its HQ in San Jose CA and is let by Tadd Matsuoka CEO who has 30 years of experience in the semi-conductor industry. VAXEL is a Xilinx partner.

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Support for UltraScale(ZCU102)