Over 60 pre-validated verification IP (VIP) blocks choose from

Using VAXEL UI, just select the VIP blocks that matched your RTL design and generate FPGA bitstream.

Interface VIP includes 22 blocks and generators in categories bellow

Data read/write interface
Asynchronous bridge (AXI to AXI/AHB/APB) and IP generator
Memory block
Register Interface and IP generator
RAM wrapper
HDMI

Debugging VIP includes 34 blocks in categories bellow

Assertion block
Wave monitor
Hash block
BFM