NEWS

Enabling Image Process ASIC HDL verification with real-size test data without suffering from slowness of Simulators or high cost of Emulators or having to learn FPGA synthesis.

AUTHOR: Yasu Sakakibara, CTO

Image Process hardware design verification requires a set of very large test data. This has become more true with the recent increase in the frame sizes from FHD to 4K, 8K, and larger. RTL designers, however, are forced to conduct design verifications with reduced-size test data for two reasons:first, because today’s Simulators take a long time to run large test data, and second, because the hardware emulation tools from the EDA vendors are just too expensive for most of the projects…………… CONTINUE READING